Vidwan-ID : 101590



  • Dr Anup Dandapat

  • Professor
  • National Institute of Technology, Meghalaya
Publications 2008 - 2023

Publications

  • 52
    Journal Articles
  • 1
    Book Chapter
  • 1
    Book
  • 40
    Conference
    Proceedings
  • 3
    Editorial
  • 1
    Review
  • 3
    Projects
  • 2
  • 51

Citations / H-Index

776 Citations
14 h-index
325 Citations

Google Scholar

Co-author Network


Expertise

Electrical and Electronic Engineering

Low power VLSI design, Low power high speed multiplier circuits, Adiabatic circuits for low power VLSI application, Low power low cost memory (SRAM, CAM, DBCAM, TCAM) design, Cyclic combinational circuits

Personal Information

Dr Anup Dandapat

Male
NIT Meghalaya Bijni Complex, Laitumkhrah
East Khasi Hills, Meghalaya, India - 793003


Experience

  • Professor

    National Institute of Technology, Meghalaya

  • Associate Professor

    Department of Electronics And Communication Engineering

    National Institute of Technology, Meghalaya


Qualification

  • Ph.D

    Jadavpur University


Doctoral Theses Guided

2022

Match-Line Controlled Content Addressable Memory: Low-Power and High-Speed Searching

Sheikh Wasmir Hussain, NIT Meghalaya

2021

Precharge Free Content Addressable Memory: Binary and Ternary

Telajala Venkata Mahendra, NIT Meghalaya

2020

Low Power High Resolution Flash- SAR ADC: Standalone and Hybrid Architectures

Farhana Begum, NIT Meghalaya

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2022

Match-Line Controlled Content Addressable Memory: Low-Power and High-Speed Searching

Sheikh Wasmir Hussain, NIT Meghalaya

2021

Precharge Free Content Addressable Memory: Binary and Ternary

Telajala Venkata Mahendra, NIT Meghalaya

2020

Low Power High Resolution Flash- SAR ADC: Standalone and Hybrid Architectures

Farhana Begum, NIT Meghalaya

2019

Implementation of the Computational Arithmetic Operations for Signal Processing Applications.

Deepak Kumar, NIT Meghalaya

2018

High Density Ternary Content Addressable Memory: Storage and Sensing

Sandeep Mishra, NIT Meghalaya

2017

Circuit level optimization techniques for low power VLSI Design

Vinay Kumar, NIT Meghalaya

2014

Efficient VLSI Implementation of Arithmetic Operations Based on Vedic Mathematics

Prabir Saha, IIEST Shibpur

2012

Study of Low Power High Performance Digital Circuits using Nano Scale MOS Structure

Dibyendu Kayal, Jadavpur University

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Membership In Professional Bodies

2015

IEEE

Senior Member

2015

IEEE

Senior Member

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Research Projects

Special Manpower Development Project

Funding Agency : MeitY

Ultra Low Power Multi Array 64K X 16 Dual Bit Associative Memory with partial matching Capability.

Funding Agency : SERB

A “Study Project Proposal” on Dynamic Reconfigurable Implementation of Cryptographic Algorithms on FPGA Platform.

Funding Agency : DeitY

Special Manpower Development Project

Funding Agency : MeitY

Ultra Low Power Multi Array 64K X 16 Dual Bit Associative Memory with partial matching Capability.

Funding Agency : SERB

A “Study Project Proposal” on Dynamic Reconfigurable Implementation of Cryptographic Algorithms on FPGA Platform.

Funding Agency : DeitY

Read Less